清理现场 创建新的milkyway库
file delete -force $my_mw_lib
create_mw_lib $my_mw_lib -open -technology $tech_file -mw_reference_library
"STD/Apollo/SMIC18STDLIBM6 IO/Apollo/SMIC18IOLIB_L_M6"
导入设计网表
import_designs $verilog_file -format verilog -top $top_design
设置寄生参数模型文件 wc,bc,tf映射文件
set_tlu_plus_files -max_tluplus $tlup_max -min_tluplus $tlup_min \
-tech2itf_map $tlup_map
推导PG连接,自动将标准单元的PG引脚连接到芯片的全局电源和地网络上
derive_pg_connection -power_net $PWR_NAME -power_pin $PWR_NAME -ground_net $GND_NAME \
-ground_pin $GND_NAME
derive_pg_connection -power_net $PWR_NAME -ground_net $GND_NAME -tie
check_mv_design -power_nets
读约束文件
read_sdc $sdc_file
ckpt: 将状态保存为setuped单元
save_mw_cel -as setuped
# 打开上一步的单元
open_mw_lib aes_ASIC.MW
open_mw_cel setuped
PAD约束
source -echo -v scripts/pad_cell.cons.tcl
# detailed:
# create 4 corner + P/G PAD on_demand
#create_cell {...} PLCORNER_D / PLVSSC / PLVDDC / PLVSSH /PLVDDH
#set_pad_physical_constraints -pad_name "corner_ul/ur/lr/ll" -side 1/2/3/4
#set_pad_physical_constraints -pad_name "" -side 1/2/3/4(ltru) -order ...
再次连接IO PAD的P/G
derive_pg_connection…
定义芯片的物理尺寸和核心区域
create_floorplan -control_type width_and_height -core_width 1560 -core_height 1560 \
-left_io2core 200 -right_io2core 200 -top_io2core 200 -bottom_io2core 200 \
-start_first_row -flip_first_row
在IO PAD间插入填充单元
insert_pad_filler -cell {PLFILLER30 PLFILLER20 PLFILLER10 PLFILLER5 PLFILLER1 \
PLFILLER01 PLFILLER005} -overlap_cell "PLFILLER0005"
再次连接P/G
derive_pg_connection…
ckpt: 将状态保存为floorplan_pad_assigned单元
save_mw_cel -as floorplan_pad_assigned
设置Floorplan阶段的放置策略
set_fp_placement_strategy \
-auto_grouping high \
-macros_on_edge on \
-silver_size 10 \
-virtual_IPO on
宏单元周围设置边距
set_keepout_margin -type hard -all_macros -outer {10 10 10 10}
初步放置宏单元和标准单元
create_fp_placement -timing_driven -no_hierarchy_gravity
ckpt: 将状态保存为floorplan_placed单元
save_mw_cel -as floorplan_placed
再次连接P/G
derive_pg_connection…
设置电源轨道约束
set_fp_rail_constraints -add_layer {M5} -direction horizontal ...
set_fp_rail_constraints -add_layer {M6} -direction vertical ...
set_fp_rail_constraints -set_ring -horizontal_ring_layer { M3 } -vertical_ring_layer { M4 } ...
综合电源网络并创建
set_fp_rail -nets {VDD GND} -voltage_supply 1.98 -synthesize_power_plan \
-power_budget 350 -pad_masters { PLVDDC PLVSSC }
commit_fp_rail
进行静态IR Drop分析
analyze_ir_drop -nets {VDD GND} -voltage_supply 1.98 -power_budget 350 \
-pad_masters { PLVDDC PLVSSC }
提示M5和M6层已被电源网络大量占用
set_pnet_options -complete "M5 M6"
电源网络创建后的再放置
create_fp_placement -timing_driven -no_hierarchy_gravity
执行全局布线
route_zrt_global
ckpt: 将状态保存为floorplanned单元
save_mw_cel -as floorplanned
写DEF(Design Exchange Format) 文件
write_def -version 5.6 -placed -all_vias -blockages -routed_nets \
-specialnets -rows_tracks_gcells -output design_data/aes_ASIC.def
M6更高层金属不用于信号布线
set_ignored_layers -max_routing_layer M6
理想时钟树
set_ideal_network [all_fanout -flat -clock_tree]
来自tf的特殊布线规则(Non-Default Rule, NDR)
应用到时钟网络
define_routing_rule 2X_SPACING -spacings {M3 0.56 M4 0.76 M5 0.66 M6 1.02}
set_clock_tree_options -clock_tree [all_clocks] -routing_rule 2X_SPACING -layer_list "M3 M6"
低功耗优化
set_optimize_pre_cts_power_options -low_power_placement true
执行详细布局和优化
place_opt -area_recovery -power
ckpt: 将状态保存为placed单元
save_mw_cel -as placed
ckpt: 拷贝为clock_opt单元
copy_mw_cel -from placed -to clock_opt
open_mw_cel clock_opt
设置CTS skew, uncertainty和可用cell
set_clock_tree_options -target_skew 0.1
set_clock_uncertainty 0.1 [all_clocks]
set_clock_tree_references -references {INVCLKHD1X INVCLKHD1X ... BUFCLKHD80X}
另一个NDR
define_routing_rule CLOCK_DOUBLE_SPACING \
-spacings {M3 0.50 M4 0.76 M5 0.66 M6 1.02}
set_clock_tree_options -routing_rule CLOCK_DOUBLE_SPACING ...
设置延迟计算模型
set_delay_calculation_options -preroute awe -postroute arnoldi -routed_clock_arnoldi \
-arnoldi_effort medium -awe_effort medium
执行时钟树综合
clock_opt -only_cts -no_clock_route
ckpt: 将状态保存为clock_opt_cts单元
save_mw_cel -as clock_opt_cts
移除理想时钟假设
remove_ideal_network [all_fanout -flat -clock_tree]
寄生参数提取
extract_rc
CTS优化修复Hold违例
set_fix_hold [all_clocks]
clock_opt -only_psyn -area_recovery -optimize_dft -no_clock_route
ckpt: 将状态保存为clock_opt_psyn单元
save_mw_cel -as clock_opt_psyn
执行时钟网络布线
route_zrt_group -all_clock_nets -reuse_existing_global_route true
ckpt: 将状态保存为clock_opt_route单元
save_mw_cel -as clock_opt_route
检查理想网络、高扇出 略
布线禁区
set_net_routing_rule -reroute freeze -rule default [get_nets POS_E3V]
create_route_guide -coordinate {{0} {116.9 2193.3}} -no_signal_layers {M1 M2 V2 M3 V4 M4 V5 M5 M6} -no_preroute_layers {G1 M1 M2 M3 M4 M5 M6}
冗余过孔,优化过孔连线
set_route_zrt_common_options -post_detail_route_redundant_via_insertion high
set_route_zrt_common_options -optimize_wire_via_effort_level medium
执行预布线
preroute_instances -ignore_pads -ignore_macros -ignore_cover_cells -skip_pad_pins_touching_pad_side_boundaries
preroute_standard_cells -remove_floating_pieces
执行布线
# 初始布线
route_opt -initial_route_only
# 后布线优化 + 功耗优化
route_opt -skip_initial_route -power
再次连接P/G
derive_pg_connection…
verify_zrt_route # 检查布线结果
ckpt: 将状态保存为route_opt_final单元
save_mw_cel -as route_opt_final
ckpt: 拷贝为chip_finish单元
copy_mw_cel -from route_opt_final -to chip_finish
open_mw_cel chip_finish
DFM: 扩展导线间距、加宽导线
spread_zrt_wires
widen_zrt_wires
DFM: 天线效应修复
# 识别ANT
set_route_zrt_detail_options -antenna true -insert_diodes_during_routing true
# 增量布线修复ANT
route_zrt_detail -incremental true
# 修复引入的DRC
route_opt -incremental
DFM: 填充单元满足密度要求
# INSERT STANDARD CELL FILLERS #
insert_stdcell_filler -cell_with_metal {FILLER64HD ... FILLER1HD} -connect_to_power $PWR_NAME -connect_to_ground $GND_NAME ...
# INSERT REDUNDANT VIAS #
insert_zrt_redundant_vias -effort medium
# INSERT METAL FILL #
insert_metal_filler -routing_space 1 -timing_driven
签核
# LVS
verify_zrt_lvs -ignore_floating_port -check_open_locator -ignore_metal_without_net_name
# Verilog 网表
write_verilog -no_physical_only_cells aes_ASIC.sim.vg
write_verilog -diode_ports -pg aes_ASIC_lvs.vg
# 寄生参数
write_parasitics -format SPEF -output aes_ASIC.spef
# Stream
set_write_stream_options -child_depth 255 -map_layer .../gdsLayers.map ...
write_stream -cells chip_finish_final aes_ASIC.gdsii